Paper Abstract and Keywords |
Presentation |
2013-03-07 14:30
Performance Evaluation of a Combination of Sum-Product and Two-bit Bit Flipping Decoding Algorithms Koh Matsushita, Hiroshi Kamabe (Gifu Univ.) IT2012-72 ISEC2012-90 WBS2012-58 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A Bit-Flipping algorith which uses only two bits for each node has been proposed. The bit error probability of the method is very close to that of the sum-product algorithm for binary symmetric channels at high SNR region.
We show that the performance of a combination of sum-product decoding and two-bit bit flipping decoding when the method is applied to additive white gaussian noise channels. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
LDPC codes / Sum-Product Algorithm / Bit-Flipping Algorithm / Bias Terms / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 112, no. 460, IT2012-72, pp. 65-70, March 2013. |
Paper # |
IT2012-72 |
Date of Issue |
2013-02-28 (IT, ISEC, WBS) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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IT2012-72 ISEC2012-90 WBS2012-58 |
Conference Information |
Committee |
IT ISEC WBS |
Conference Date |
2013-03-07 - 2013-03-08 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kwansei Gakuin Univ., Osaka-Umeda Campus |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
joint meeting of IT, ISEC, and WBS |
Paper Information |
Registration To |
IT |
Conference Code |
2013-03-IT-ISEC-WBS |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Performance Evaluation of a Combination of Sum-Product and Two-bit Bit Flipping Decoding Algorithms |
Sub Title (in English) |
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Keyword(1) |
LDPC codes |
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Sum-Product Algorithm |
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Bit-Flipping Algorithm |
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Bias Terms |
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1st Author's Name |
Koh Matsushita |
1st Author's Affiliation |
Gifu University (Gifu Univ.) |
2nd Author's Name |
Hiroshi Kamabe |
2nd Author's Affiliation |
Gifu University (Gifu Univ.) |
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Speaker |
Author-1 |
Date Time |
2013-03-07 14:30:00 |
Presentation Time |
25 minutes |
Registration for |
IT |
Paper # |
IT2012-72, ISEC2012-90, WBS2012-58 |
Volume (vol) |
vol.112 |
Number (no) |
no.460(IT), no.461(ISEC), no.462(WBS) |
Page |
pp.65-70 |
#Pages |
6 |
Date of Issue |
2013-02-28 (IT, ISEC, WBS) |
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