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Paper Abstract and Keywords
Presentation 2012-03-07 09:15
A Power Grid Optimization Algorithm Considering by NBTI
Yoriaki Nagata, Masahiro Fukui (Ritsumeikan Univ.), Shuji Tsukiyama (Chuo Univ.) VLD2011-132
Abstract (in Japanese) (See Japanese page) 
(in English) With the advent of super deep submicron age and high integration, the circuit was concerned about the impact of timing degradation by Negative bias temperature instability (NBTI) and EM which is a reliability problem of LSI. NBTI is a phenomenon in which the performance of a transistor deteriorates depending on the temperature and the transistor switching frequency. In the manufacturing process generations, it will be expected that timing degradation by NBTI becomes non-ignorable. Conventionally, power grid optimization algorithms has been proposed by IR drop and EM as their object function. This paper proposes a high reliable power grid optimization technique in which timing degradation by NTBI of after-manufacture five or ten years is taken into consideration.
Keyword (in Japanese) (See Japanese page) 
(in English) NBTI / timing degradation / power grid optimization / risk function / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 450, VLD2011-132, pp. 73-78, March 2012.
Paper # VLD2011-132 
Date of Issue 2012-02-28 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2011-132

Conference Information
Committee VLD  
Conference Date 2012-03-06 - 2012-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English) B-con Plaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Methodologies for System-on-a-chip 
Paper Information
Registration To VLD 
Conference Code 2012-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Power Grid Optimization Algorithm Considering by NBTI 
Sub Title (in English)  
Keyword(1) NBTI  
Keyword(2) timing degradation  
Keyword(3) power grid optimization  
Keyword(4) risk function  
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1st Author's Name Yoriaki Nagata  
1st Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
2nd Author's Name Masahiro Fukui  
2nd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
3rd Author's Name Shuji Tsukiyama  
3rd Author's Affiliation Chuo University (Chuo Univ.)
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Speaker Author-1 
Date Time 2012-03-07 09:15:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2011-132 
Volume (vol) vol.111 
Number (no) no.450 
Page pp.73-78 
#Pages
Date of Issue 2012-02-28 (VLD) 


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