IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2012-03-07 14:35
Performance of the Evaluation of a Variable-Latency-Circuit on FPGA
Yuuta Ukon, Kenta Ando, Atsushi Takahashi (Osaka Univ) VLD2011-141
Abstract (in Japanese) (See Japanese page) 
(in English) The performance of integrated circuits, which are the base of ICT nowaday,
is always requested to be improved.
In de facto standard of current integrated circuits,
the performance of integrated circuits is determined by the maximum delay
between flip-flops
since the global clock is inputted to flip-flops simultaneously and the latency
is fixed at a unit time.
Therefore, the reduction of the maximum delay has been pursued, however, it
approaches the limit.
In this paper, we discuss variable-latency circuits which use the error
detection/correction mechanism
where the performance is not necessarily bounded by the maximum delay.
In experiments, ripple-carry-adder (RCA) is implemented onto FPGA as a
variable-latency circuit,
and its behavior is verified and its performance is evaluated.
As the results, we confirm that the behavior is correct and that
the performance is improved compared to a conventional implementation.
Keyword (in Japanese) (See Japanese page) 
(in English) Error Detection/Correction(EDC) / Variable Latency Circuit(VLC) / delay error / effective clock period / design constraint / Field Programmable Gate Array / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 450, VLD2011-141, pp. 127-132, March 2012.
Paper # VLD2011-141 
Date of Issue 2012-02-28 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2011-141

Conference Information
Committee VLD  
Conference Date 2012-03-06 - 2012-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English) B-con Plaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Methodologies for System-on-a-chip 
Paper Information
Registration To VLD 
Conference Code 2012-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Performance of the Evaluation of a Variable-Latency-Circuit on FPGA 
Sub Title (in English)  
Keyword(1) Error Detection/Correction(EDC)  
Keyword(2) Variable Latency Circuit(VLC)  
Keyword(3) delay error  
Keyword(4) effective clock period  
Keyword(5) design constraint  
Keyword(6) Field Programmable Gate Array  
Keyword(7)  
Keyword(8)  
1st Author's Name Yuuta Ukon  
1st Author's Affiliation Osaka University (Osaka Univ)
2nd Author's Name Kenta Ando  
2nd Author's Affiliation Osaka University (Osaka Univ)
3rd Author's Name Atsushi Takahashi  
3rd Author's Affiliation Osaka University (Osaka Univ)
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2012-03-07 14:35:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2011-141 
Volume (vol) vol.111 
Number (no) no.450 
Page pp.127-132 
#Pages
Date of Issue 2012-02-28 (VLD) 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan