Paper Abstract and Keywords |
Presentation |
2012-03-06 15:05
High-Level Synthesis for Mixed Behavioral-Level/RTL Design Descriptions Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo) VLD2011-128 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
It is widely known that high-level synthesis technology can improve the design productivity dramatically by raising the level of abstraction. However, when the design specification is given at cycle level, e.g. controller and communication circuits, it must be designed in register transfer level (RTL) description. In practice, new products are designed by enhancing the existing RTL design instead of designing from scratch. Therefore, it is desirable that a design can be described partly at behavioral-level and partly at register transfer level. In this paper, we first propose a model and its representation of mixed behavioral-level and RTL design. More specifically, we extend finite state machine with datapath (FSMD), which models an RTL design, by introducing a superstate which models a behavioral-level design. We also propose a high-level synthesis method for a mixed-level design. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
High-level synthesis / behavioral-level description / register-transfer-level description / finite state machine with datapath (FSMD) / incremental high-level synthesis / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 450, VLD2011-128, pp. 49-54, March 2012. |
Paper # |
VLD2011-128 |
Date of Issue |
2012-02-28 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2011-128 |
Conference Information |
Committee |
VLD |
Conference Date |
2012-03-06 - 2012-03-07 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
B-con Plaza |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Methodologies for System-on-a-chip |
Paper Information |
Registration To |
VLD |
Conference Code |
2012-03-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
High-Level Synthesis for Mixed Behavioral-Level/RTL Design Descriptions |
Sub Title (in English) |
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Keyword(1) |
High-level synthesis |
Keyword(2) |
behavioral-level description |
Keyword(3) |
register-transfer-level description |
Keyword(4) |
finite state machine with datapath (FSMD) |
Keyword(5) |
incremental high-level synthesis |
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1st Author's Name |
Hiroaki Yoshida |
1st Author's Affiliation |
University of Tokyo (Univ. of Tokyo) |
2nd Author's Name |
Masahiro Fujita |
2nd Author's Affiliation |
University of Tokyo (Univ. of Tokyo) |
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Speaker |
Author-1 |
Date Time |
2012-03-06 15:05:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2011-128 |
Volume (vol) |
vol.111 |
Number (no) |
no.450 |
Page |
pp.49-54 |
#Pages |
6 |
Date of Issue |
2012-02-28 (VLD) |
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