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Paper Abstract and Keywords
Presentation 2008-06-13 12:50
Application of the massively parallel embedded processor (MX) to real-time image processing
Hiroyuki Yamasaki, Takeaki Sugimura, Hideyuki Noda, Osamu Yamamoto, Yoshihiro Okuno, Kazutami Arimoto (Renesas)
Abstract (in Japanese) (See Japanese page) 
(in English) We developed the massively parallel embedded processor core (MX core) for the SoC(System on Chip) building in as an accelerator for the multimedia processing. It realizes both high flexibilities and high performance ability while achieving small silicon area and low power consumption. This MX core achieves 100 times or more speed-up by applying the filter processing and the FFT operation to a basic image data processing compared with general-purpose RISC processor. Moreover, it reports on implementing a real-time demonstration using these image data processing.
Keyword (in Japanese) (See Japanese page) 
(in English) massively parallel processing / SIMD / processor / image processing / real-time processing / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 86, SIS2008-20, pp. 33-38, June 2008.
Paper # SIS2008-20 
Date of Issue 2008-06-05 (SIS) 

Conference Information
Committee SIS  
Conference Date 2008-06-12 - 2008-06-13 
Place (in Japanese) (See Japanese page) 
Place (in English)  
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Topics (in English)  
Paper Information
Registration To SIS 
Conference Code 2008-06-SIS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Application of the massively parallel embedded processor (MX) to real-time image processing 
Sub Title (in English)  
Keyword(1) massively parallel processing 
Keyword(2) SIMD 
Keyword(3) processor 
Keyword(4) image processing 
Keyword(5) real-time processing 
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1st Author's Name Hiroyuki Yamasaki  
1st Author's Affiliation Renesas Technology Corp. (Renesas)
2nd Author's Name Takeaki Sugimura  
2nd Author's Affiliation Renesas Technology Corp. (Renesas)
3rd Author's Name Hideyuki Noda  
3rd Author's Affiliation Renesas Technology Corp. (Renesas)
4th Author's Name Osamu Yamamoto  
4th Author's Affiliation Renesas Technology Corp. (Renesas)
5th Author's Name Yoshihiro Okuno  
5th Author's Affiliation Renesas Technology Corp. (Renesas)
6th Author's Name Kazutami Arimoto  
6th Author's Affiliation Renesas Technology Corp. (Renesas)
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Speaker
Date Time 2008-06-13 12:50:00 
Presentation Time 25 
Registration for SIS 
Paper # IEICE-SIS2008-20 
Volume (vol) IEICE-108 
Number (no) no.86 
Page pp.33-38 
#Pages IEICE-6 
Date of Issue IEICE-SIS-2008-06-05 


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