IEICE Technical Committee Submission System
Conference Paper's Information
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2008-06-13 14:00
Implementation of Simultaneous Video Decoding on Multicore Processor
Yuki Kawamura, Yasutake Manabe, Takao Onoye (Osaka Univ.), Kazuto Ohara, Hiroyuki Okada, Ikuo Keshi (Sharp)
Abstract (in Japanese) (See Japanese page) 
(in English) A number of digital video contents have been used through various media such as optical disc storage, digital television, and Internet. Moreover, DVD/HDD recorders are widespread and growing in capacity to store more contents. Such a situation causes strong demands for novel systems utilizing large amount of digital video streams including simultaneous video browsing and video search systems. In this paper, an implementation of simultaneous video decoding on Cell Broadband Engine is reported aiming at multiple video display systems. By introducing a set of mechanisms to reduce decoding complexity, simultaneous decoding of 40 MPEG-2 HL (1,920$\times$1,080) streams is attained.
Keyword (in Japanese) (See Japanese page) 
(in English) MPEG-2 / Cell Broadband Engine / Parallel processing / Low complexity decode / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 86, SIS2008-23, pp. 51-56, June 2008.
Paper # SIS2008-23 
Date of Issue 2008-06-05 (SIS) 

Conference Information
Committee SIS  
Conference Date 2008-06-12 - 2008-06-13 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SIS 
Conference Code 2008-06-SIS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementation of Simultaneous Video Decoding on Multicore Processor 
Sub Title (in English)  
Keyword(1) MPEG-2 
Keyword(2) Cell Broadband Engine 
Keyword(3) Parallel processing 
Keyword(4) Low complexity decode 
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Yuki Kawamura  
1st Author's Affiliation Osaka University (Osaka Univ.)
2nd Author's Name Yasutake Manabe  
2nd Author's Affiliation Osaka University (Osaka Univ.)
3rd Author's Name Takao Onoye  
3rd Author's Affiliation Osaka University (Osaka Univ.)
4th Author's Name Kazuto Ohara  
4th Author's Affiliation Sharp Corporation (Sharp)
5th Author's Name Hiroyuki Okada  
5th Author's Affiliation Sharp Corporation (Sharp)
6th Author's Name Ikuo Keshi  
6th Author's Affiliation Sharp Corporation (Sharp)
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
Speaker
Date Time 2008-06-13 14:00:00 
Presentation Time 25 
Registration for SIS 
Paper # IEICE-SIS2008-23 
Volume (vol) IEICE-108 
Number (no) no.86 
Page pp.51-56 
#Pages IEICE-6 
Date of Issue IEICE-SIS-2008-06-05 


[Return to Top Page]

[Return to IEICE Home Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan