IEICE Technical Committee Submission System
Conference Paper's Information
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2008-05-09 10:00
[Invited Talk] NoizeProblems in LSI Design:Challenges and Approaches
Makoto Nagata (Kobe Univ.)
Abstract (in Japanese) (See Japanese page) 
(in English) Digital designs intending high-speed and low-power consumption necessarily deal with dynamic power supply noise, for successful implementation of low-voltage operation, fine-grained power domain management, as well as dynamic voltage-frequency scaling. Analog designs for precision and low-voltage operation need to be tolerant again gt substrate crosstalk in SoC. Chip and board co-design of LSI systems is strongly required for lower noise and higher EMC performance. Challenges and approaches against noise problems in LSI design include in-depth understanding of noise behaviors and design flows for integrity.
Keyword (in Japanese) (See Japanese page) 
(in English) Power supply noise / Substrate noise / Signal Integrity / On-Chip Monitoring / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 23, VLD2008-7, pp. 1-6, May 2008.
Paper # VLD2008-7 
Date of Issue 2008-05-01 (VLD) 

Conference Information
Committee VLD IPSJ-SLDM  
Conference Date 2008-05-08 - 2008-05-09 
Place (in Japanese) (See Japanese page) 
Place (in English) Kobe Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Design, etc. 
Paper Information
Registration To IPSJ-SLDM 
Conference Code 2008-05-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) NoizeProblems in LSI Design:Challenges and Approaches 
Sub Title (in English)  
Keyword(1) Power supply noise 
Keyword(2) Substrate noise 
Keyword(3) Signal Integrity 
Keyword(4) On-Chip Monitoring 
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Makoto Nagata  
1st Author's Affiliation Kobe University (Kobe Univ.)
2nd Author's Name  
2nd Author's Affiliation ()
3rd Author's Name  
3rd Author's Affiliation ()
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
Speaker
Date Time 2008-05-09 10:00:00 
Presentation Time 60 
Registration for IPSJ-SLDM 
Paper # IEICE-VLD2008-7 
Volume (vol) IEICE-108 
Number (no) no.23 
Page pp.1-6 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2008-05-01 


[Return to Top Page]

[Return to IEICE Home Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan