| 講演抄録／キーワード |
| 講演名 |
2005-09-15 15:00
Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew
○Zhangcai Huang（Waseda Univ.）・Atsushi Kurukawa（STAC）・Yasuaki Inoue（Waseda Univ.） |
| 抄録 |
（和） |
In deep submicron designs, predicting
gate slews and delays for interconnect loads is vitally
important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of interconnect loads. Many Ceff algorithms have been proposed to compute gate delay
of interconnect loads. However, less work has been
done to develop a Ceff algorithm which can accurately
predict gate slew. In this paper, we propose a novel
method for calculating the Ceff of interconnect load
for gate slew. The simulation results demonstrate a
significant improvement in accuracy. |
| （英） |
In deep submicron designs, predicting
gate slews and delays for interconnect loads is vitally
important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of interconnect loads. Many Ceff algorithms have been proposed to compute gate delay
of interconnect loads. However, less work has been
done to develop a Ceff algorithm which can accurately
predict gate slew. In this paper, we propose a novel
method for calculating the Ceff of interconnect load
for gate slew. The simulation results demonstrate a
significant improvement in accuracy. |
| キーワード |
（和） |
Static Timing Analysis / gate slew / interconnect load / effective capacitance / / / / |
| （英） |
Static Timing Analysis / gate slew / interconnect load / effective capacitance / / / / |
| 文献情報 |
信学技報, vol. 105, no. 276, NLP2005-44, pp. 31-36, 2005年9月. |
| 資料番号 |
NLP2005-44 |
| 発行日 |
2005-09-08 (CAS, NLP) |
| ISSN |
Print edition: ISSN 0913-5685 |
| PDFダウンロード |
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