後藤 源助

1. H. Takahashi, S. Sato, G. Goto, T. Nakamura, H. Kikuchi, and T. Shirato, "A 240K
   Transistor CMOS Array with Flexible Allocation of Memory and Channels," IEEE
   Journal of Solid-State Circuits, Vol. SC-20, No. 5, pp. 1012-1017, Oct. 1985.
   
   

2. H. Kubosawa, G. Goto, S. Tsutsumi, Y. Suehiro, and T. Shirato, "Layout Approaches
   to High-Density Channelless Masterslice," IEEE Custom Integrated Circuits Conf.
   (CICC), Portland, Oregon, Proc. pp.48-51, May 1987．
   

3. G. Goto, A. Inoue, R. Ohe, S. Kashiwakura, S. Mitarai, T. Tsuru, and T. Izawa, "A
   4.1-ns Compact 54×54-b Multiplier Utilizing Sign-Select Booth Encoders," IEEE
   Journal of Solid-State Circuits, Vol. 32, No. 11, pp. 1676-1682, Nov. 1997.