秋濃俊郎

1. T. Akino, M. Shimode, Y. Kurashige, T. Negishi:
   "Circuit Simulation and Timing Verification Based on
   MOS/LSI Mask Information," Proceedings of 16th
   Design Automation Conference, San Diego, pp.88-94, June 1979.
   
   
2. T. Akino, T. Kajita, A. Tanaka, H. Miyamoto, Y. Mitsuyasu:
   "Electronic Rule Checking for Structured VLSI Physical Design,"
   Proceedings of IEEE International Conference on Circuits and Computers,
   New York, pp.447-450, September 28 〜 October 1, 1982.
   
   

3. M. Toyonaga, S.-T. Yang, I. Shirakawa, T. Akino:
   "A New Approach of Fractal-Analysis Based Module Clustering
   for VLSI Placement," IEICE Trans. Fundamentals, Vol. E77-A, No. 12,
   pp.2045-2053, December 1994.