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  1. ã“c˜aGC
    h˜_—ƒ‚ƒWƒ…[ƒ‹‚Ì”z’uŽè–@‚Æ‚»‚Ì•]‰¿,h
    “dŽqî•ñ’ʐMŠw‰ï˜_•¶ŽiD), ‚U‚O|D,@‚QC‚‚D‚P‚T‚P|‚P‚T‚WCFeb.@‚P‚X‚V‚VD

  2. K. Ueda, H.Kitazawa,
    "CHAMP: Chip Floor Plan for Hierarchical VLSI Design,"
    IEEE Trans on CAD, Vol.4, No.1, pp.12-22, Jan. 1985.

  3. K. Ueda, H. Kitazawa,
    "Top-down Layout for Hierarchical CustomDesign,"
    IEEE Design & Test, Vol. 4, No. 6, pp.22-29, Jan. 1987.





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