“dŽqî•ñ’ÊMŠw‰ï @
ƒƒS

ã“c@˜aG

  1. ã“c˜aGC
    h˜_—ƒ‚ƒWƒ…[ƒ‹‚Ì”z’uŽè–@‚Æ‚»‚Ì•]‰¿,h
    “dŽqî•ñ’ÊMŠw‰ï˜_•¶ŽiD), ‚U‚O|D,@‚QC‚‚D‚P‚T‚P|‚P‚T‚WCFeb.@‚P‚X‚V‚VD

  2. K. Ueda, H.Kitazawa,
    "CHAMP: Chip Floor Plan for Hierarchical VLSI Design,"
    IEEE Trans on CAD, Vol.4, No.1, pp.12-22, Jan. 1985.

  3. K. Ueda, H. Kitazawa,
    "Top-down Layout for Hierarchical CustomDesign,"
    IEEE Design & Test, Vol. 4, No. 6, pp.22-29, Jan. 1987.





| TOP | MENU | BACK |

(C) Copyright 2000 IEICE.All rights reserved.