樹下
行三
- Kozo Kinoshita and Kewal K. Saluja,
"Built-in Testing of Memory Using an On-Chip Compact Testing
Scheme,"
IEEE Transactions on Computers, Vol.C-35, No.10, pp.862-870, October
1986.
-
Wen Xiaoqing and Kozo Kinoshita,
"A Testable Design of Logic Circuits under Highly Observable
Condition,"
IEEE Transaction on Computers, Vol.41, No.5, pp.654-659, May 1992.
-
Toshiyuki Maeda and Kozo Kinoshita,
"Precise Test Generation for Resistive Bridging Fault of CMOS
Combinational
Circuits,"
pp. 510-519, Proceedings of International Test Conference, October
2000.
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