電子情報通信学会  
ロゴ

田丸 啓吉
  1. "Operational-Amplifier Compilation with Performance Optimization",
    IEEEJ. of Solid-State
    Circuits, Vol.25, No.2, PP.466-473( Apr. 1990)
  2. "An Architecture for High Speed Array Multiplier",
    IEICE Trans.Fundamentals, Vol. E76-A,
    No. 8, PP.1326-1333 (Aug. 1993)

  3. "Architecture and Performance Evaluation of a New Functional Memory : Fu
    nctional Memory
    for Addition",
    IEICE Trans. Fundamentals, Vol. E83-A, No. 12, PP. 2400-2408 (Dec. 2000)





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