Special Issue on the 1995 Symposium on VLSI Circuits
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(Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996)
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 . FOREWORD ........................................................ 881
        A.Iwata and I.Young

PAPERS
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[Communications]

 . A 2.5-Gb/s 15-mW Clock Recovery Circuit ......................... 883
        B.Razavi

 . 46 Gb/s DEMUX, 50 Gb/s MUX, and 30 GHz Static Frequency Divider in
   Silicon Bipolar Technology ...................................... 892
        A.Felder, M.Mo��ller, J.Popp, J.Bo��ck, and H.-M.Rein

[Logic]

 . A 250-622 MHz Deskew and Jitter-Suppressed Clock Buffer Using
   Two-Loop Architecture ........................................... 898
        S.Tanoi, T.Tanabe, K.Takahashi, S.Miyamoto, and M.Uesugi

 . An 80-MOPS-Peak High-Speed and Low-Power-Consumption 16-b Digital
   Signal Processor ................................................ 905
        H.Kabuo, M.Okamoto, I.Tanaka, H.Yasoshima, S.Marui, M.Yamasaki,
        T.Sugimura, K.Ueda,T.Ishikawa, H.Suzuki, and R.Asahi

 . A 286 MHz 64-b Floating Point Multiplier with Enhanced CG Operation
            ........................................................ 915
        H.Makino, H.Suzuki, H.Morinaka, Y.Nakase, K.Mashiko, and T.Sumi

 . An Efficient Charge Recovery Logic Circuit ...................... 925
        Y.Moon and D.-K.Jeong

[Interface Circuits]

 . A Low Power and High Speed Data Transfer Scheme with Asynchronous
   Compressed Pulse Width Modulation for AS-Memory ................. 934
        T.Yamauchi, Y.Morooka, and H.Ozaki

 . Capacitance Coupling Immune, Transient Sensitive Accelerator for
   Resistive Interconnect Signals of Subquarter Micron ULSI ........ 942
        T.Iima, M.Mizuno, T.Horiuchi, and M.Yamashina

[Memory]

 . A 90-MHz 16-Mb System Integrated Memory with Direct Interface to CPU
            ........................................................ 948
        K.Dosaka, A.Yamazaki, N.Watanabe, H.Abe, J.Ohtani, T.Ogawa,
        K.Ishihara, and M.Kumanoya

 . A Current Direction Sense Technique for Multiport SRAM's ........ 957
        M.Izumikawa and M.Yamashina

 . Driving Source-Line Cell Architecture for Sub-1-V High-Speed
   Low-Power Applications .......................................... 963
        H.Mizuno and T.Nagano

 . Fault-Tolerant Designs for 256 Mb DRAM .......................... 969
        T.Kirihata, Y.Watanabe, H.Wong, J.K.DeBrosse, M.Yoshida,
        D.Katoh, S.Fujii, M.R.Wordeman,P.Poechmueller, S.A.Parke, and
        Y.Asao

 . A 286 mm2 256 Mb DRAM with �~32 Both-Ends DQ .................... 978
        Y.Watanabe, H.Wong, T.Kirihata, D.Kato, J.K.DeBrosse, T.HARA,
        M.Yoshida, H.Mukai,K.N.Quader, T.Nagai, P.Poechmueller,
        P.Pfefferl, M.R.Wordeman, and S.Fujii

 . A Mixed-Mode Voltage Down Converter with Impedance Adjustment
   Circuitry for Low-Voltage High-Frequency Memories ............... 986
        T.Ooishi, Y.Komiya, K.Hamade, M.Asakura, K.Yasuda, K.Furutani,
        T.Kato, H.Hidaka,and H.Ozaki

 . SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga
   Scale Memories .................................................. 997
        S.Kuge, F.Morishita, T.Tsuruda, S.Tomishima, M.Tsukude,
        T.Yamagata, and K.Arimoto

 . Cell-Plate-Line/Bit-Line Complementary Sensing (CBCS) Architecture
   for Ultra Low-Power DRAM's ..................................... 1003
        T.Hamamoto, Y.Morooka, M.Asakura, and H.Ozaki

 . A Double-Level-Cth Select Gate Array Architecture for Multilevel
   NAND Flash Memories ............................................ 1013
        K.Takeuchi, T.Tanaka, and H.Nakamura

 . ABSTRACTS (IEICE Trans., Vol.J79-C-I, J79-C-II, No.7 in Japanese)
            ....................................................... 1021