Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems ========================================================================================== . FOREWORD ........................................................ 273 Hiroshi TANIMOTO and Hisashi YAMADA PAPERS ====== . High-Speed Adaptive Noise Canceller with Parallel Block Structure ........................................................ 275 Kiyoyasu MARUYAMA, Chawalit BENJANGKAPRASERT, Nobuaki TAKAHASHI,and Tsuyoshi TAKEBE . Design of FIR Digital Filters Using Estimates of Error Function over CSD Coefficient Space ........................................... 283 Mitsuhiko YAGYU, Akinori NISHIHARA, and Nobuo FUJII . Filter Bank Implementation of the Shift Operation in Orthonormal Wavelet Bases ................................................... 291 Achim GOTTSCHEBER and Akinori NISHIHARA . Network Reflection and Transmission Coefficients for the Interconnection of Multi-Port Multi-Line Junction Networks ...... 297 Iwata SAKAGAMI . Estimation of Short-Circuit Power Dissipation for Static CMOS Gates ........................................................ 304 Akio HIRATA, Hidetoshi ONODERA, and Keikichi TAMARU . Power and Area Minimization by Reorganizing CMOS Complex-Gates .. 312 Masayoshi TACHIBANA, Sachiko KUROSAWA, Reiko NOJIMA, Naohito KOJIMA,Masaaki YAMADA, Takashi MITSUHASHI, and Nobuyuki GOTO . A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints ................. 321 Nozomu TOGAWA, Masao SATO, and Tatsuo OHTSUKI . Single Chip Implementation of MPEG2 Decoder for HDTV Level Pictures ........................................................ 330 Takao ONOYE, Toshihiro MASAKI, Yasuo MORIMOTO, Yoh SATO, Isao SHIRAKAWA,and Kenji MATSUMURA . A Precise Event-Driven MOS Circuit Simulator .................... 339 Tetsuro KAGE, Hisanori FUJISAWA, Fumiyo KAWAFUJI, and Tomoyasu KITAURA . Optimal Instruction Set Design through Adaptive Database Generation ........................................................ 347 Nguyen Ngoc BINH, Masaharu IMAI, Akichika SHIOMI, and Nobuyuki HIKICHI . Implicit Representation and Manipulation of Binary Decision Diagrams ........................................................ 354 Hitoshi YAMAUCHI, Nagisa ISHIURA, and Hiromitsu TAKAHASHI . An Analysis on Minimum Searching Principle of Chaotic Neural Network ........................................................ 363 Masaya OHTA, Kazumichi MATSUMIYA, Akio OGIHARA, Shinobu TAKAMATSU,and Kunio FUKUNAGA LETTERS ======= . Evolutionary Digital Filtering Based on the Cloning and Mating Reproduction .................................................... 370 Masahide ABE, Masayuki KAWAMATA, and Tatsuo HIGUCHI . Design of Multiplierless 2-D State-Space Digital Filters over a Powers-of-Two Coefficient Space ................................. 374 Young-Ho LEE, Masayuki KAWAMATA, and Tatsuo HIGUCHI . A Stabilizing Control Method Based on Distributed Circuit Model for Electric Power Systems .......................................... 378 Atsushi HAMADA, Kiyoshi TAKIGAWA, Kensuke KAWASAKI, and Hiromu ARIYOSHI . Pulse Width Modulated Control of Chaotic Systems ................ 381 Keiji KONISHI, Masahiro OTANI, and Hideki KOKAME Regular Section =============== PAPERS ====== [Acoustics] . Speech Enhancement Using Microphone Array with Multi-Stage Processing ...................................................... 386 Yuchang CAO, Sridha SRIDHARAN, and Miles MOODY [Digital Signal Processing] . Interference Cancellation with Interpolated FFT ................. 395 Hiroomi HIKAWA and Vijay K. JAIN [Nonlinear Problems] . Chaos and Related Bifurcation Phenomena from a Simple Hysteresis Network ......................................................... 402 Kenya JIN'NO LETTER ====== [Communication Theory and Signals] . G/D/1 Queueing Analysis by Discrete Time Modeling ............... 415 Kenji NAKAGAWA . ABSTRACTS (IEICE Trans., Vol.J79-A, No.3 in Japanese) ........... 418