Special Issue on Verification, Test and Diagnosis of VLSI Systems ================================================================= . FOREWORD ........................................................ 789 Hideo FUJIWARA PAPERS ====== . Towards Verification of Bit-Slice Circuits\\Time-Space Modal Model Checking Approach\\ ........................................... 791 Hiromi HIRAISHI . Temporal Verification of Real-Time Systems ...................... 796 SeLrgio V.CAMPOS, Edmund M.CLARKE, Wilfredo MARRERO, Marius MINEA and Hiromi HIRAISHI . A New Conformance Testing Technique for Localization of Multiple Faults in Communication Protocols ............................... 802 Yoshiaki KAKUDA, Hideki YUKITOMO, Shinji KUSUMOTO and Tohru KIKUNO . Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis ............................................ 811 Seiji KAJIHARA, Rikiya NISHIGAYA, Tetsuji SUMIOKA and Kozo KINOSHITA . A Single Bridging Fault Location Technique for CMOS Combinational Circuits ........................................................ 817 Koji YAMAZAKI and Teruhiko YAMADA . A Study for Testability of Redundant Faults in Combinational Circuits Using Delay Effects .................................... 822 Xiangqiu YU, Hiroshi TAKAHASHI and Yuzo TAKAMATSU . Testing of k-FR Circuits under Highly Observable Condition ...... 830 Wen XIAOQING, Hideo TAMAMOTO and Kozo KINOSHITA . The Effect of CMOS VLSI IDDq Measurement on Defect Level ........ 839 Junichi HIRASE and Masanori HAMADA . A Method of Current Testing for CMOS Digital and Mixed-Signal LSIs ........................................................ 845 Yukiya MIURA and Sachio NAITO . Very Fast Fault Simulation for Voltage Stuck-at Faults in Analog/Digital Mixed Circuit .................................... 853 Shigeharu TESHIMA, Naoya CHUJO and Ryuta TERASHIMA . Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement ...................... 861 Hiroyuki YOTSUYANAGI, Seiji KAJIHARA and Kozo KINOSHITA . A Practical Test System with a Fuzzy Logic Controller ........... 868 Takeshi KOYAMA and Ryuji OHMURA . The Number of Elements in Minimum Test Set for Locally Exhaustive Testing of Combinational Circuits with Five Outputs ............. 874 Tokumi YOKOHIRA, Toshimi SHIMIZU, Hiroyuki MICHINISHI, Yuji SUGIYAMA and Takuji OKAMOTO . Design of Autonomous TPG Circuits for Use in Two-Pattern Testing 882 Kiyoshi FURUYA, Seiji SEKI and Edward J.McCLUSKEY . Stuck-Open Fault Detectabilities of Various TPG Circuits for Use in Two-Pattern Testing ............................................. 889 Kiyoshi FURUYA, Susumu YAMAZAKI and Masayuki SATO Regular Section =============== PAPERS ====== [Automata, Languages and Theory of Computing] . The Firing Squad Synchronization Problem in Defective Cellular Automata ........................................................ 895 Martin KUTRIB and Roland VOLLMAR [Algorithm and Computational Complexity] . The Complexity of Drawing Tree-Structured Diagrams .............. 901 Kensei TSUCHIDA [Image Processing, Computer Graphics and Pattern Recognition] . Global Interpolation in the Segmentation of Handwritten Characters Overlapping a Border ............................................ 909 Satoshi NAOI, Maki YABUKI, Atsuko ASAKAWA and Yoshinobu HOTTA . Direct Reconstruction of Planar Surfaces by Stereo Vision ....... 917 Yasushi KANAZAWA and Kenichi KANATANI . ABSTRACTS (IEICE Trans., Vol.J78-D-I, J78-D-II, No.7 in Japanese) ........................................................ 923