Special Issue on LSI Memory Device, Circuit, Architecture and Application
=========================================================================
Technologies for Multimedia Age
===============================
 . FOREWORD ........................................................ 765
        Masahide TAKADA

INVITED PAPERS
==============
 . ULSI Memory for Multimedia Applications ......................... 766
        Yasuo AKATSUKA, Yoichi YANO Shigeo NIITSU and Akihiko MORINO

 . Emerging Memory Solutions for Graphics Applications ............. 773
        Katsumi SUIZU, Toshiyuki OGAWA and Kazuyasu FUJISHIMA

PAPERS
======
 . A Synchronous DRAM with New High-Speed I/O Lines Method for the
   MultiMedia Age .................................................. 782
        Yuji SAKAI, Kanji OISHI, Miki MATSUMOTO, Shoji WADA, Tadamichi
        SAKASHITA and Masahiro KATAYAMA

 . NAND-Structured Trench Capacitor Cell Technologies for 256Mb DRAM
   and Beyond ...................................................... 789
        Takeshi HAMAMOTO, Yutaka ISHIBASHI, Masami AOKI, Yoshihiko
        SAITOH and Takashi YAMADA

 . A Low-Power Synchronous SRAM Macrocell with Latch-Type Fast Sense
   Circuits ........................................................ 797
        Nobutaro SHIBATA and Mayumi WATANABE

 . PLL Timing Design Techniques for Large-Scale, High-Speed, Low-Power,
   Low-Cost SRAMs .................................................. 805
        Kazuyuki NAKAMURA, Shigeru KUHARA, Tohru KIMURA, Masahide
        TAKADA,Hisamitsu SUZUKI, Hiroshi YOSHIDA and Tohru YAMAZAKI

 . Low-Voltage Operation of a High-Resistivity Load SOI SRAM Cell by
   Reduced Back-Gate-Bias Effect ................................... 812
        Yasuo YAMAGUCHI, Jun TAKAHASHI, Takehisa YAMAGUCHI, Tomohisa
        WADA,Toshiaki IWAMATSU, Hans-Oliver JOACHIM, Yasuo INOUE,
        Tadashi NISHIMURA and Natsuro TSUBOUCHI

 . A 65ns 3V-only NAND-Flash Memory with New Verify Scheme and Folded
   Bit-Line Architecture ........................................... 818
        Hiromi NOBUKATA, Kenichi SATORI, Shinji HIRAMATSU and Hideki
        ARAKAWA

 . Design of a 3.3V Single Power-Supply 64Mbit Flash Memory with
   Dynamic Bit-Line Latch (DBL) Programming Scheme ................. 825
        Hiroshi SUGAWARA, Toshio TAKESHIMA, Hiroshi TAKADA, Yoshiaki
        S.HISAMUNE,Kohji KANAMORI, Takeshi OKAZAWA, Tatsunori MUROTANI
        and Isao SASAKI

 . Programming and Program-Verification Methods for Low-Voltage Flash
   Memories Using a Sector Programming Scheme ...................... 832
        Katsutaka KIMURA, Toshihiro TANAKA, Masataka KATO, Tetsuo
        ADACHI, Keisuke OGURA and Hitoshi KUME

 . BIST Circuit Macro Using Microprogram ROM for LSI Memories ...... 838
        Hiroki KOIKE, Toshio TAKESHIMA and Masahide TAKADA

 . New ƒ¿-Particle Induced Soft Error Mechanism in a Three Dimensional
   Capacitor Cell .................................................. 845
        Yukihito OOWAKI, Keiji MABUCHI, Shigeyoshi WATANABE, Kazunori
        OHUCHI,Jun'ichi MATSUNAGA and Fujio MASUOKA

 . Use of a Monte Carlo Wiring Yield Simulator to Optimize Design of
   Random Logic Circuits for Yield Enhancement ..................... 852
        Hideyuki FUKUHARA, Takao KOMATSUZAKI, Katsushi BOKU and Yoichi
        MIYAI

Regular Section
===============
PAPERS
======
[Integrated Electronics]

 . Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs ......... 858
        Tadaaki YAMAUCHI, Koji TANAKA, Kiyohiro FURUTANI, Yoshikazu
        MOROOKA,Hiroshi MIYAMOTO and Hideyuki OZAKI

 . 3.0Gb/s, 272mW, 8:1 Multiplexer and 4.1Gb/s, 388mW, 1:8
   Demultiplexer ................................................... 866
        Kimio UEDA, Nagisa SASAKI, Hisayasu SATO, Shunji KUBO and
        Koichiro MASHIKO

[Superconductive Electronics]

 . Frequency-Dependent Finite-Difference Time-Domain Analysis of
   High-Tc Superconducting Asymmetric Co-planar Strip Line ......... 873
        Masafumi HIRA, Yasunobu MIZOMOTO and Sadao KURAZONO

[Electronic Displays]

 . Analysis on Reduction of the Temperature Rise of Deflection Yoke
   (DY) ............................................................ 878
        Rensi MOROOKA, Yukitoshi INOUE and Katsuhiko SHIOMI

LETTER
======
[Opto-Electronics]

 . Fiber Optic Temperature Sensor Using Two Modes by Holographic Filter
            ........................................................ 885
        Manabu YOSHIKAWA and Kazuo ASAKAWA

 . ABSTRACTS (IEICE Trans., Vol.J78-C-I, J78-C-II, No.7 in Japanese)
            ........................................................ 887