Special Issue on the 1994 VLSI Circuits Symposium
=================================================
iJoint Issue with the IEEE Journal of Solid-State Circuits, Vol.30, No.4 April 1995)
=====================================================================================
 . FOREWORD ........................................................ 587
        K.O'Connor and A.Iwata

PAPERS
======
 . ATM in B-ISDN Communication Systems and VLSI Realization ........ 589
        T.Koinuma and N.Miyaho

 . Asynchronous Transfer Mode Switching LSI Chips with 10-Gb/s Serial
   I/O Ports ....................................................... 596
        S.Hino, M.Togashi, and K.Yamasaki

 . A CMOS Serial Link for Fully Duplexed Data Communication ........ 601
        K.Lee, S.Kim, G.Ahn, and D.-K.Jeong

 . A 256-Element Associative Parallel Processor .................... 613
        F.P.Herrmann and C.G.Sodini

 . Future Directions in Microprocessor Technology .................. 619
        M.P.Marks

 . Cache-Processor Coupling: A Fast and Wide On-Chip Data Cache Design
            ........................................................ 623
        M.Motomura, T. Inoue, T.Yamada, and A.Konagaya

 . A Wide-Bandwidth Low-Voltage PLL for PowerPCTM Microprocessors .. 631
        J.Alvarez, H.Sanchez, G.Gerosa, and R.Countryman

 . A Multiplexer-Based Architecture for High-Density, Low-Power Gate
   Arrays .......................................................... 640
        R.J.Landers, S.S.Mahant-Shetti, and C.Lemonds

 . Data-Dependent Logic Swing Internal Bus Architecture for
   Ultralow-Power LSI's ............................................ 645
        M.Hiraki, H.Kojima, H.Misawa, T.Akazawa, and Y.Hatano

 . A Programmable Clock Generator that Uses Noise Shaping and Its
   Application in Switched-Capacitor Filters ....................... 651
        P.J.Hurst and B.C.Rothenberg

 . An All-Digital Phase-Locked Loop With 50-Cycle Lock Time Suitable
   for High-Performance Microprocessors ............................ 660
        J.Dunning, G.Garcia, J.Lundberg, and E.Nuckolls

 . An Asymptotically Zero Power Charge-Recycling Bus Architecture for
   Battery-Operated Ultrahigh Data Rate ULSI's ..................... 671
        H.Yamauchi, H.Akamatsu, and T.Fujita

 . Half-Swing Clocking Scheme for 75% Power Saving in Clocking
   Circuitry ....................................................... 680
        H.Kojima, S.Tanaka, and K.Sasaki

 . Present and Future Directions for Multichip Module Technologies . 684
        T.Sudo

 . A 13-b 10-Msample/s ADC Digitally Calibrated with Oversampling
   Delta-Sigma Converter ........................................... 691
        T.-H.Shu, B.-S.Song, and K.Bacrania

 . A High Resolution Multibit Sigma-Delta Modulator with Individual
   Level Averaging ................................................. 701
        F.Chen and B.H.Leung

 . A Median Peak Detecting Analog Signal Processor for Hard Disk Drive
   Servo ........................................................... 709
        K.Nagaraj, S.H.Lewis, R.W.Walden, G.E.Offord, R.S.Shariatdoust,
        J.A.Sabnis, R.O.Peruzzi,J.R.Barner, J.Plany, R.P.Mento,
        V.A.Rakshani, and R.W.Hull

 . An Automatic Temperature Compensation of Internal Sense Ground for
   Subquarter Micron DRAM's ........................................ 719
        T.Ooishi, Y.Komiya, K.Hamade, M.Asakura, K.Yasuda, K.Furutani,
        H.Hidaka, H.Miyamoto,and H.Ozaki

 . A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense
   Amplifiers ...................................................... 728
        K.Ishibashi, K.Takasugi, K.Komiyaji, H.Toyoshima, T.Yamanaka,
        A.Fukami, N.Hashimoto, N.Ohki, A.Shimizu, T.Hashimoto,
        T.Nagano, and T.Nishida

 . A 2.6-ns Wave-Pipelined CMOS SRAM with Dual-Sensing-Latch Circuits
            ........................................................ 735
        S.Tachibana, H.Higuchi, K.Takasugi, K.Sasaki, T.Yamanaka, and
        Y.Nakagome

 . A 0.65-ns, 72-kb ECL-CMOS RAM Macro for a 1-Mb SRAM ............. 739
        H.Nambu, K.Kanetani, Y.Idei, T.Masuda, K.Higeta, M.Ohayashi, 
        M.Usami, K.Yamaguchi,T.Kikuchi, T.Ikeda, K.Ohhata, T.Kusunoki, 
        and N.Homma

 . A Source Sensing Technique Applied to SRAM Cells ................ 748
        K.J.O'Connor

 . ABSTRACTSiIEICE Trans., Vol. J78-C-I, J78-C-II, No.6 in Japanesej
            ........................................................ 760