Special Section on VLSI Design and CAD Algorithms ================================================= . FOREWORD ....................................................... 1987 Toshiro AKINO PAPERS and LETTERS ================== . High-Level VLSI Design Specification Validation Using Algorithmic Debugging ...................................................... 1988 Jiro NAGANUMA, Takeshi OGURA and Tamio HOSHINO . Datapath Scheduling for Behavioral Description with Conditional Branches ....................................................... 1999 Akihisa YAMADA, Toshiki YAMAZAKI, Nagisa ISHIURA, Isao SHIRAKAWA and Takashi KAMBE . A Reduced Scan Shift Method for Sequential Circuit Testing ..... 2010 Yoshinobu HIGAMI, Seiji KAJIHARA and Kozo KINOSHITA . Analysis of Pulse Responses of Multi-Conductor Transmission Lines by a Partitioning Technique ....................................... 2017 Yuichi TANJI, Lingge JIANG and Akio USHIDA . Maple: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays ........... 2028 Nozomu TOGAWA, Masao SATO and Tatsuo OHTSUKI . A Graph Bisection Algorithm Based on Subgraph Migration ........ 2039 Kazunori ISOMOTO, Yoshiyasu MIMASA, Shin'ichi WAKABAYASHI, Tetsushi KOIDE and Noriyoshi YOSHIDA . A New Approach of Fractal-Analysis Based Module Clustering for VLSI Placement ...................................................... 2045 Masahiko TOYONAGA, Shinh-Tsung YANG, Isao SHIRAKAWA and Toshiro AKINO . A Floorplanning Method with Topological Constraint Manipulation in VLSI Building Block Layout [Letter] ............................ 2053 Tetsushi KOIDE, Yoshinori KATSURA, Katsumi YAMATANI, Shin'ichi WAKABAYASHI and Noriyoshi YOSHIDA . A Global Router Optimizing Timing and Area for High-Speed Bipolar LSIs ........................................................... 2058 Ikuo HARADA, Yuichiro TAKEI and Hitoshi KITAZAWA . A Fast Vectorized Maze Routing Algorithm on a Supercomputer .... 2067 Yoshio MIKI . A Modified Genetic Channel Router .............................. 2076 Akio SAKAMOTO, Xingzhao LIU and Takashi SHIMAMOTO . A Multi-Layer Channel Router Using Simulated Annealing ......... 2085 Masahiko TOYONAGA, Chie IWASAKI, Yoshiaki SAWADA and Toshio AKINO Regular Section =============== PAPERS ====== [Nonlinear Phenomena and Analysis] . Chaos Synchronization in Discrete-Time Dynamical Systems and Its Applications ................................................... 2092 Makoto ITOH and Hiroyuki MURAKAMI [Ultrasonics] . Piezoelectric Ceramic Transformer for Power Supply Operating in Thickness Extensional Vibration Mode ........................... 2098 Osamu OHNISHI, Yasuhiro SASAKI, Toshiyuki ZAITSU, Hiromi KISHIE and Takeshi INOUE LETTERS ======= [Algorithm, Data Structures and Computational Complexity] . A Note on a Completely Linearly Nested Context-Free Grammar and Its Generalization ................................................. 2106 Tetsuo MORIYA [Neural Networks] . Power Law Slowdown of the Neural Learning ...................... 2109 Hideyuki CAOTEAU, Tatsuhiro NAKAJIMA, Hiroshi NUNOKAWA and Nobuko FUCHIKAMI . Neural Networks for Digital Sequential Circuits ................ 2112 Hiroshi NINOMIYA and Hideki ASAI [Nonlinear Phenomena and Analysis] . Control of Chua's Circuit by Switching a Resistor .............. 2116 Keiji KONISHI, Hiroaki KAWABATA and Yoji TAKEDA . ABSTRACTS(IEICE Trans., Vol. J77-A, No.12 in Japanese) ......... 2120 . 1994 INDEX ..................................................... 2126