Special Issue on Super Chip for Intelligent Integrated Systems
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 . FOREWORD ....................................................... 1021
        Michitaka KAMEYAMA

INVITED PAPERS
==============
 . Overview of the Super Database Computer (SDC-I) ................ 1023
        Masaru KITSUREGAWA, Weikang YANG, Satoshi HIRANO, Masanobu
        HARADA, Minoru NAKAMURA, Kazuhiro SUZUKI, Takayuki TAMURA and
        Mikio TAKAGI

PAPERS
======
 . The Concept of Four-Terminal Devices and Its Significance in the
   Implementation of Intelligent Integrated Circuits .............. 1032
        Tadahiro OHMI and Tadashi SHIBATA

 . Low-Power 8-Valued Cellular Array VLSI for High-Speed Image
   Processing ..................................................... 1042
        Takahiro HANYU, Maho KUWAHARA and Tatsuo HIGUCHI

 . A Discrete Fourier Analyzer Based on Analog VLSI Technology .... 1049
        Shoji KAWAHITO, Kazuyuki TAKEDA, Takanori NISHIMURA and
        Yoshiaki TADOKORO

 . Quantizer Neuron Chip (QNC) with Multichip Extendable Architecture
            ....................................................... 1057
        Masakatsu MARUYAMA, Hiroyuki NAKAHIRA, Shiro SAKIYAMA,
        Toshiyuki KOHDA, Susumu MARUNO and Yasuharu SHIMEKI

 . A Memory-Based Recurrent Neural Architecture for Chip Emulating
   Cortical Visual Processing ..................................... 1065
        Luigi RAFFO, Silvio P. SABATINI, Giacomo INDIVERI, Giovanni
        NATERI and Giacomo M. BISIO

 . 7.5MFLIPS Fuzzy Microprocessor Using SIMD and Logic-in-Memory
   Structure ...................................................... 1075
        Mamoru SASAKI and Fumio UENO

 . Graceful Degradation for Multiprocessor Realization of Maximally
   Flat FIR Digital Filters ....................................... 1083
        Saed SAMADI, Akinori NISHIHARA and Nobuo FUJII

 . Performance Evaluation of a Processing Element for an On-Chip
   Multiprocessor ................................................. 1092
        Masafumi TAKAHASHI, Hiroshige FUJII, Emi KANEKO, Takeshi
        YOSHIDA, Toshinori SATO, Hiroyuki TAKANO, Haruyuki TAGO, Seigo
        SUZUKI and Nobuyuki GOTO

 . High-Level Synthesis of VLSI Processors for Intelligent Integrated
   Systems ........................................................ 1101
        Yasuaki SAWANO, Bumchul KIM and Michitaka KAMEYAMA

 . Design of a CAM-Based Collision Detection VLSI Processor for
   Robotics ....................................................... 1108
        Masanori HARIYAMA and Michitaka KAMEYAMA

 . A VLSI-Oriented Model-Based Robot Vision Processor for 3-D
   Instrumentation and Object Recognition ......................... 1116
        Yoshifumi SASAKI and Michitaka KAMEYAMA

 . Design of a Reconfigurable Parallel Processor for Digital Control
   Using FPGAs .................................................... 1123
        Yoshichika FUJIOKA, Michitaka KAMEYAMA and Nobuhiro TOMABECHI

Regular Section
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PAPERS
======
[Integrated Electronics]

 . Ultimate Lower Bound of Power for MOS Integrated Circuits and Their
   Applications ................................................... 1131
        Kunihiro ASADA and Mike LEE

[Opto-Electronics]

 . Amplification Characteristics of Waveguide Type Optical Amplifier
   Using Nd Doped Garnet Thin Film ................................ 1138
        Mitsuhiro WADA and Yasumitsu MIYAZAKI

 . ABSTRACTS (IEICE Trans., Vol.J77-C-I, J77-C-II, No.7 in Japanese)
            ....................................................... 1146