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No 214163
標題(和) 400ppmの送受信周波数偏差に対応可能なシリアルATA用PHY
標題(英) A Low-Jitter 1.5-GHz and Large-EMI reduction 10-dBm Spread-Spectrum Clock Generator for Serial-ATA
研究会名(和) 回路とシステム, 通信方式, 信号処理
研究会名(英) Circuits and Systems, Communication Systems, Signal Processing
開催年月日 2012-03-08
終了年月日 2012-03-09
会議種別コード 5
共催団体名(和)
資料番号 CAS2011-129, SIP2011-149, CS2011-121
抄録(和)
抄録(英) A low-jitter and large-EMI-reduction spread spectrum clock generator (SSCG) for Serial-ATA (SATA) was developed. A low-jitter voltage-controlled oscillator (VCO) with a high-frequency limiter was developed to prevent the SSCG from malfunctioning. This VCO achieved far less jitter than that of a conventional VCO. An auto-calibration technique suitable for this VCO was developed to prevent the SSCG from degrading performance because of process variations. A SATA-PHY using a technique for calibrating the SSCG was developed to use an inexpensive but large frequency-variation reference oscillator. This technique was used to calibrate the SSCG output-signal frequency. This is achieved by shifting an SSCG divide ratio by utilizing the difference between an SSCG output signal frequency and a received signal frequency. These techniques were fabricated in 0.13- and 0.15-um CMOS processes. The proposed SSCG achieved a 10.0-dB reduction in EMI. The variation in the rms jitter at 1.5 GHz with spread-spectrum clocking was reduced from 2.1-7.8 ps to 1.9-3.3 ps by the proposed autocalibration technique. The proposed SATA PHY achieved less than 400-ppm production-frequency tolerance of reference clocks.
収録資料名(和) 電子情報通信学会技術研究報告
収録資料の巻号 Vol.111, No.465,466,467
ページ開始 125
ページ終了 130
キーワード(和) SSCG,CDR,PLL,シリアルATA
キーワード(英) SSCG,CDR,PLL,Serial-ATA
本文の言語 JPN
著者(和) 川本高司
著者(ヨミ) カワモト タカシ
著者(英) Takashi Kawamoto
所属機関(和) 日立
所属機関(英) Hitachi
著者(和) 鈴木正人
著者(ヨミ) スズキ マサト
著者(英) Masato Suzuki
所属機関(和) ルネサスエレクトロニクス
所属機関(英) Reness Electronics

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