| No | 207440 |
|---|---|
| 標題（和） | 組み込みネットワークアプリのためのXilinx Spartan3 FPGAを用いたローコストTCP/IPハードウェア実現 |
| 標題（英） | A Modular Low Cost Hardware TCP/IP Stack Implementation Adding Direct Network Capabilities to Same On-Chip Embedded Applications Using Xilinx Spartan3 FPGA |
| 研究会名（和） | 通信方式, 信号処理, 回路とシステム |
| 研究会名（英） | Communication Systems, Signal Processing, Circuits and Systems |
| 開催年月日 | 2011-03-03 |
| 終了年月日 | 2011-03-04 |
| 会議種別コード | 5 |
| 共催団体名（和） | |
| 資料番号 | CAS2010-128, SIP2010-144, CS2010-98 |
| 抄録（和） | As multi-processor based computers and electronic devices become the norm,\r\na further emphasis is made on achieving tasks by means of low power parallel processing.\r\nFurthermore, with the growth of Internet-based rich multimedia applications, \r\nthese tasks would often require high speed network capabilities readily available.\r\nAn FPGA, unlike ASIC implementations which are difficult to adopt for their lack of standards,\r\nwould allow us to develop flexible and power-efficient high-speed processing systems capable\r\nof addressing the tasks at hand. \r\n\r\nIn previous works we have introduced a remotely reconfigurable hardware/software complex system which is capable of exchanging virtual hardware circuits over Ethernet, as well as a proof of concept client-server architecture based web application that compresses and streams video in hardware, achieving a full-color VGA size (24bits RGB, 640x480 pixels) 20 fps video stream with throughput of 10.8Mbps. \r\n\r\n In this paper we propose a hardware TCP/IP stack implementation as an extension to this model, to enable Internet connectivity and to accelerate networking multimedia transmission. \r\nThis TCP/IP stack is both modular, allowing direct connection of embedded applications without CPU or PCI bus resource usage through a common on-chip bus architecture, and extensible as it consists of independent blocks that can easily be changed in order to support future changes in protocols. \r\nThis framework simplifies the development of networking applications since Internet Protocol (IP) packets, UDP datagrams and TCP segments are all directly processed in hardware. \r\n\r\nA software application needs only to interact with a memory buffer to use the network resources of the system.\r\n The applications of this modular TCP/IP stack vary in a wide range of devices such as multimedia content based devices, robotics and network security appliances. These \r\napplications will be able not only to gather and distribute information, but \r\nalso to be reconfigured through the web.\r\nThe proposed system is implemented in Xilinx\'s low-end Spartan3 FPGA, which operates at 66MHz with achieved throughput of 100Mbps. |
| 抄録（英） | As multi-processor based computers and electronic devices become the norm,\r\na further emphasis is made on achieving tasks by means of low power parallel processing.\r\nFurthermore, with the growth of Internet-based rich multimedia applications, \r\nthese tasks would often require high speed network capabilities readily available.\r\nAn FPGA, unlike ASIC implementations which are difficult to adopt for their lack of standards,\r\nwould allow us to develop flexible and power-efficient high-speed processing systems capable\r\nof addressing the tasks at hand. \r\n\r\nIn previous works we have introduced a remotely reconfigurable hardware/software complex system which is capable of exchanging virtual hardware circuits over Ethernet, as well as a proof of concept client-server architecture based web application that compresses and streams video in hardware, achieving a full-color VGA size (24bits RGB, 640x480 pixels) 20 fps video stream with throughput of 10.8Mbps. \r\n\r\n In this paper we propose a hardware TCP/IP stack implementation as an extension to this model, to enable Internet connectivity and to accelerate networking multimedia transmission. \r\nThis TCP/IP stack is both modular, allowing direct connection of embedded applications without CPU or PCI bus resource usage through a common on-chip bus architecture, and extensible as it consists of independent blocks that can easily be changed in order to support future changes in protocols. \r\nThis framework simplifies the development of networking applications since Internet Protocol (IP) packets, UDP datagrams and TCP segments are all directly processed in hardware. \r\n\r\nA software application needs only to interact with a memory buffer to use the network resources of the system.\r\n The applications of this modular TCP/IP stack vary in a wide range of devices such as multimedia content based devices, robotics and network security appliances. These \r\napplications will be able not only to gather and distribute information, but \r\nalso to be reconfigured through the web.\r\nThe proposed system is implemented in Xilinx\'s low-end Spartan3 FPGA, which operates at 66MHz with achieved throughput of 100Mbps. |
| 収録資料名（和） | 電子情報通信学会技術研究報告 |
| 収録資料の巻号 | Vol.110, No.439,440,441 |
| ページ開始 | 155 |
| ページ終了 | 160 |
| キーワード（和） | |
| キーワード（英） | FPGA,TCP/IP,UDP,Network on chip,hw/sw complex system,Ethernet,Reconfigurable hardware |
| 本文の言語 | ENG |
| 著者（和） | ナダヴ ベルグシュタイン |
| 著者（ヨミ） | タムコウ ハカル |
| 著者（英） | Nadav Bergstein |
| 所属機関（和） | 東京農工大学 |
| 所属機関（英） | Tokyo University of Agriculture and Technology |
| 著者（和） | 田向権 |
| 著者（ヨミ） | セキネ マサトシ |
| 著者（英） | Hakaru Tamukoh |
| 所属機関（和） | 東京農工大学 |
| 所属機関（英） | Tokyo University of Agriculture and Technology |
| 著者（和） | 関根優年 |
| 著者（ヨミ） | セキネ マサトシ |
| 著者（英） | Masatoshi Sekine |
| 所属機関（和） | 東京農工大学 |
| 所属機関（英） | Tokyo University of Agriculture and Technology |