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Technical Committee onVLSI Design Technologies
There is a remarkable development of the recent VLSI (Very Large Scale
Integration) technologies. It is said that 10 billion transistors will
be put in one chip in year 2015. With the development, the design of the
VLSI chip will become more and more complicated and on a large scale. It
is indispensable to tackle many problems in a VLSI design overall. In
this technical committee, we are making a mission to contribute to the
society through a wide range of research activities, in which we also
consider the deployment of new applicable fields from basic research,
about the design techniques of VLSI.

In designing the future VLSI, specially by accumulating the whole system
on one chip as system LSI, fusion of various technologies, such as
digital/analog mixed-signal technologies, and software skills, are
indispensable. In this study for VLSI applications, researchers gather
broadly and discuss actively on parallel/distribution algorithms as the
methodology for VLSI designs, and various kinds of design automations
from a system level design to a layout design, such as EDA (Electronic
Design Automation) techniques, CAD (Computer Aided Design) techniques,
and fundamental algorithms and data structures, which supports them. In
addition, by making a special feature theme, we are having active study
meetings in cooperation not only with the technical committees of IEICE
on "architecture", "circuits and systems", "digital signal processing",
"reconfigurable systems", "integrated circuits", and "dependable
computing" but also with the associated groups of the Information
Processing Society of Japan and the Japan Society of Applied Physics.
The main areas of research fields dealt concretely are as follows:
VLSI Design methodology
VLSI Architecture
Hardware / software co-design
Functional composition
Logic composition
Low power consumption design
Simulation (system level, functions, logics, circuits, processes,devices, etc.)
Hardware/software co-simulation
Formal verification
Design For Testability (test pattern generation and simple test design)
Floor plan, arrangement, outline wiring, and detailed wiring
Layout verification
Analog circuits design
Cell/modular design
CAD Framework
In addition, VLSI Design and CAD algorithms related fields.
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