Achievement Award

  Needless to say, the computer is the most important device in the information society, and Shuichi Sakai, the recipient, is one of the leading people who proposed and developed general purpose massively parallel computers in the world. He proposed a computation model and computer architecture naturally integrating computation and communication, and showed its performance by developing and operating actual prototype machines such as a highly parallel computer EM-4 (Fig.1) and massively parallel computer RWC-1 (Fig.2). In addition, he proposed the Circular Omega network and CCCB network for module interconnections, and proposed and implemented a load distribution mechanism using the networks. The recipient first showed the world that truly efficient highly parallel processing can be realized by proposing the innovative model, architecture and mechanisms. In addition, he proposed the efficient multipath parallel processing / multithread processing / power saving pipeline, etc., as execution methods in the VLSI chip, and implemented and evaluated the processor based on them, and showed the effectiveness.
  These research results were published in top international conferences such as ISCA and MICRO, and prestigious English journals, and thus were recognized as remarkable achievements both in Japan and abroad. For this achievement, the recipient received many awards including the Japan IBM Science Award (1991), the Ichimura Prize in Science for Distinguished Achievement (1995), the IEEE Outstanding Paper Award (ICCD'95), STA Remarkable Invention (1996), SUN Distinguished Speaker Award (1997), and IPSJ Best Paper award (1991). He also received the IEICE Fellow (2011) and IPSJ Fellow (2010) for continuous contributions in this field.
  In addition, these experiences brought him three text-books: "Computer Architecture (IEICE Lecture Series)" (Corona Publishing Co. Ltd., currently 15th edition), "Introduction to Logic Circuits" (Baifukan), and "Practices of Computer Architecture" (Corona Publishing Co. Ltd..). He also wrote books such as “Protection by IT, Protecting IT -- Natural and Personal Disasters and Information Technology” (received Okawa Publication Prize, NHK Books) and "Knowledge of Safety in Information Society" (Iwanami Junior Paperbacks).
  In addition, the recipient’s students have won numerous awards such as the IEEE Computer Society Young Author Award.
   Recently the recipient focused on the importance of technologies to enhance the reliability and safety of information systems. He carried this out as a research representative in two JST CREST projects, "Dependable Information Processing Infra-structure" (2002-2008) and "Ultra Dependable VLSI by collaboration of formal verifications and architectural technologies" (2007-2013), and in the SECOM Science and Technology Foundation Grant Research "Ultra-Secure Information Systems by Integrating Information Laws, Management Methodologies and Invasion Prevention Technologies" (2013-2017). In particular, he has proposed a new attack proof technology based on the program monitoring architecture, anti-error technology through the detailed control of redundancy on a logical block, and anti-tampering technology with integrity retention architecture; all of these have been verified by prototype machines. The entire processor is implemented as an "ultra-dependable processor" by providing a management mechanism to control high safety and high reliability in a unified manner. These results were presented at the representative international conferences and IEICE journals.
   To summarize, the recipient’s pioneering and comprehensive achievements in the field of computer architecture have made extremely significant contributions to information system technologies, and thus he definitely deserves the IEICE Achievement Award.

References

1. Shuichi Sakai, Yoshinori Yamaguchi, Kei Hiraki, Yuetsu Kodama and Toshitsugu Yuba, An Architecture of a Dataflow Single Chip Processor, Proceedings of 15th International Symposium on Computer Architecture, pp.46-53 (1989).
2. Shuichi Sakai, Yuetsu Kodama and Yoshinori Yamaguchi, Prototype Implementation of a Highly Parallel Dataflow Machine EM-4, Proceedings of 5th International Parallel Processing Symposium, pp.278-286 (1991).
3. Shuichi Sakai, Yuetsu Kodama and Yoshinori Yamaguchi, Design and　Implementation of a Circular Omega Network in the EM-4, Parallel　Computing, Vol.19, No.2, pp.125-142 (1993).
4. Shuichi Sakai, Kazuaki Okamoto, Hiroshi Matsuoka, Hideo Hirono, Yuetsu Kodama and Mitsuhisa Sato, Super-Threading: Architectural and Software Mechanisms for Optimizing Parallel Computation, Proceedings of 1993 International Conference on Supercomputing, pp.251-260 (1993).
5. Shuichi Sakai, Yuetsu Kodama, Mitsuhisa Sato, Andrew Shaw, Hiroshi Matsuoka, Hideo Hirono, Kazuaki Okamoto and Takashi Yokota, Reduced Interprocessor-Communication Architecture and Its Implementation on EM-4, Parallel Computing, Vol. 21, No. 5, pp.753-769 (1995).
6. Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai: "Base Address Recognition with Data Flow Tracking for Injection Attack Detection", IEEE International Symposium on Pacific Rim Dependable Computing (PRDC 2006), pp.165-172 (2006).
7. Shuichi Sakai, Masahiro Goshima and Hidetsugu Irie: Ultra Dependable Processor, IEICE Transactions on Electronics Vol. E91-C, No.9, pp.1386-1393 (2008).
8. Ryota Shioya, Kazuo Horio, Masahiro Goshima, and Shuichi Sakai: Register Cache System not for Latency Reduction Purpose, IEEE Int'l Symposium on Microarchitecture (MICRO-43), pp.301―312 (2010).
9. Naruki KURATA, Ryota SHIOYA, Masahiro GOSHIMA, and Shuichi Sakai: Address Order Violation Detection with Parallel Counting Bloom Filters, IEICE Transactions on Electronics, Vol. E98.C , No. 7, pp. 580-593 (2015).
10. Mizuki Miyanaga, Hidetsugu Irie, Shuichi Sakai: Accelerating Integrity Verification on Secure Processors by Promissory Hash, 2017 IEEE 22nd Pacific Rim International Symposium on Dependable Computing (PRDC), pp. 22-29 (2017).